1. Field of the Invention
The present invention relates to the field of computer systems, in particular, microprocessor based portable computer systems. More specifically, the present invention is related to the cache memory on these computer systems.
2. Art Background
Typically the central processing unit (CPU) in a computer system, including the CPU in a microprocessor based portable computer system, operates at a substantially faster speed than the main memory of the computer system. Most computer systems provide cache memory which can operate at a higher speed than the main memory to buffer the data and the instructions between the main memory and the high speed CPU. At any particular point in time, the cache memory stores a subset of the data and instructions in main memory.
During read cycles, data and instructions are fetched from the cache memory if they are currently stored in the cache memory (read cache hits). Otherwise (read cache misses), they are retrieved from the main memory and stored in the cache memory as well as provided to the CPU. Similarly, during write cycles, data are written into the cache memory if they are currently stored in the cache memory (write cache hits). Otherwise (write cache misses), they are either not written into the cache memory (no write allocate) or written into the cache memory after forcing a cache line update (write allocate). Furthermore, data are written into the main memory either immediately (write through) or when a cache line is reallocated (write back).
As the speed of CPUs continues to get faster, various performance motivated approaches have been developed to make cache hits faster or reduce cache miss penalty, thereby further reducing CPU idle time and improving system performance. Well known examples are virtual addressing to make cache hits faster, early re-start and out-of-order fetching to reduce read miss penalty, use of write buffer to reduce write miss penalty, and use of two level caches to reduce read/write miss penalty. In the case of the two level cache approach, typically the first level cache is made small enough to match the clock cycle time of the CPU while the second level cache is made large enough to capture many fetches that would otherwise have to go to main memory.
For further description of cache memory, cache performance problems and improvement techniques, see J. L. Hennessy, and D. A. Patterson, Computer Architecture--A Quantitative Approach, pp. 402-461, (Morgan Kaufmann, 1990).
With the advent of microprocessor based portable computer systems, due to the importance of power consumption to these computer systems, the design of cache memory on these computer systems takes on a new dimension, since every access to main memory consumes power. If not for its complexity, write back cache memory would have been ideal for these computer systems, since it consumes less power by not accessing the main memory until a cache line is reallocated or as specified by the cache coherency protocol. Notwithstanding the additional accesses to main memory and therefore more power consumption, write through cache memory remains the favored approach for microprocessor based portable computer systems because of its simplicity in implementation, as compared to write back cache memory.
Thus, it is desirable to be able to reduce power consumption on a computer system, particularly on a microprocessor based portable computer system, without having to forsake the simple to implement write through cache memory. Therefore, it is desirable to reduce power consumption on a computer system having a write through cache memory by reducing write accesses to main memory. The reduction in write accesses to main memory is to be achieved in a manner such that the power consumption savings by reduced write accesses to main memory are not negated by offsetting increases in power consumption by additional hardware. It is further desirable that the reduction in write accesses to main memory and therefore power consumption is achieved with minimal increase in performance penalty. As will be disclosed, these and other desirable results are the objects achieved by the cache memoir hierarchy of the present invention.